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In lower power systems, Hierarchical Value Cache refers to the hierarchical arrangement of Value Caches (VCs) in such a fashion that lower level VCs observe higher hit-rates, but undergo more switching activity on VC hits. The organization is similar to Memory Hierarchy, where lower-level chaches enjoy higher hit rates, but longer hit latencies. The architecture for Hierarchical Value Cache is mainly organized along two approaches: Hierarchical Unified Value Cache (HUVC) and Hierarchical Combinational Value Cache (HCVC). ==Hierarchical Unified Value Cache== This architecture of Value Cache employs all value caches storing full data values, with larger value caches in the lower levels of the hierarchy. This architecture suffers from high area overhead, but reduces the bus switching activity. The cache in HUVC in managed by LRU policy, with each VC storing 32-bit values. For incoming data, it is simultaneously checked with the VC on each level, with the uppermost VC hit getting encoded. Each hit at the ''¡''''th'' level of the HUVC incurs ''i'' bits switching activity. By switching any bit of 32-bit data bus, we can get (32!)/((32-''i'')!''i''!) numbers. That is, we could have (32!)/((32-''i'')!''i''!) entries. However, it would require complicated logic to map VC indexes to bus values. For easy VC index encoding, we partition the data bus into ''i'' segments and switch one bit in each segment. Thus, the HUVC scheme requires ''n'' control signals, where ''n'' is the depth of the VC hierarchy. The ''i''-''th'' control signal switched to indicate that the VC of level ''i'' hits. For 4-level HUVC, and 32-bit data bus, the total VC size is 22.4KB. The size of the VC is too large to be feasible in practice. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Hierarchical value cache」の詳細全文を読む スポンサード リンク
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